Topography simulation for structural analysis using cell advancing method

In this paper, we propose a novel method for topography simulation in micro-electronic processes such as deposition and etching processes. The proposed scheme comprises of calculating the forward and backward movement of the surface and converting the cell structure into a tetrahedral mesh structure with topological information. Memory requirements are mitigated through a dynamic allocating scheme, which takes only the surface cells under consideration. For the removal of cells, a fixed time step is employed while volume remains in the surface cells. A spillover algorithm has also been devised in order to consider the case when more volume has to be removed from a cell during a single time step. Our proposed scheme was applied to the cases such as the construction of a TFT-LCD structure, ROM and a DRAM cell. A numerical simulator was interfaced with the topography simulator in order to investigate the successful meshing operation form the cell structure. For exemplary application, parasitic capacitances were extracted from a test wafer structure having 4 metal lines embedded in two types of non-planar dielectric layer. The simulation result exhibited about maximum 8% error, which seems to be relatively small in comparison to the planar dielectric layer.